---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 19:03:01 06/22/2010 -- Design Name: -- Module Name: Processor - Structural -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Processor is Port ( clk : in STD_LOGIC; go_i : in STD_LOGIC; x_i : in STD_LOGIC_VECTOR (7 downto 0); y_i : in STD_LOGIC_VECTOR (7 downto 0); d_o : out STD_LOGIC_VECTOR (7 downto 0)); end Processor; architecture Structural of Processor is component Controller Port ( clk : in STD_LOGIC; go_i : in STD_LOGIC; x_neq_y : in STD_LOGIC; x_lt_y : in STD_LOGIC; x_ld : out STD_LOGIC; y_sel : out STD_LOGIC; x_sel : out STD_LOGIC; y_ld : out STD_LOGIC; d_ld : out STD_LOGIC); end component; component Datapath Port ( clk : in STD_LOGIC; x_sel : in STD_LOGIC; y_sel : in STD_LOGIC; x_ld : in STD_LOGIC; y_ld : in STD_LOGIC; d_ld : in STD_LOGIC; x_neq_y : out STD_LOGIC; x_lt_y : out STD_LOGIC; x_i : in STD_LOGIC_VECTOR (7 downto 0); y_i : in STD_LOGIC_VECTOR (7 downto 0); d_o : out STD_LOGIC_VECTOR (7 downto 0)); end component; signal x_ld_wire : STD_LOGIC; signal y_ld_wire : STD_LOGIC; signal d_ld_wire : STD_LOGIC; signal x_sel_wire : STD_LOGIC; signal y_sel_wire : STD_LOGIC; signal x_neq_y_wire : STD_LOGIC; signal x_lt_y_wire : STD_LOGIC; begin CTRL: Controller port map ( clk => clk, go_i => go_i, x_neq_y => x_neq_y_wire, x_lt_y => x_lt_y_wire, y_sel => x_sel_wire, x_sel => y_sel_wire, x_ld => x_ld_wire, y_ld => y_ld_wire, d_ld => d_ld_wire ); D1: Datapath port map ( clk => clk, y_sel => x_sel_wire, x_sel => y_sel_wire, x_ld => x_ld_wire, y_ld => y_ld_wire, d_ld => d_ld_wire, x_neq_y => x_neq_y_wire, x_lt_y => x_lt_y_wire, x_i => x_i, y_i => y_i, d_o => d_o ); end Structural;