-------------------------------------------------------------------------------- -- Copyright (c) 1995-2003 Xilinx, Inc. -- All Right Reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 12.1 -- \ \ Application : ISE -- / / Filename : MDCTest.vhw -- /___/ /\ Timestamp : Fri Jul 16 18:47:38 2010 -- \ \ / \ -- \___\/\___\ -- --Command: --Design Name: MDCTest_tb_0 --Device: Xilinx -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE IEEE.NUMERIC_STD.ALL; USE STD.TEXTIO.ALL; ENTITY MDCTest_tb_0 IS END MDCTest_tb_0; ARCHITECTURE testbench_arch OF MDCTest_tb_0 IS COMPONENT Processor PORT ( clk : In std_logic; go_i : In std_logic; x_i : In std_logic_vector (7 DownTo 0); y_i : In std_logic_vector (7 DownTo 0); d_o : Out std_logic_vector (7 DownTo 0) ); END COMPONENT; SIGNAL clk : std_logic := '0'; SIGNAL go_i : std_logic := '0'; SIGNAL x_i : std_logic_vector (7 DownTo 0) := "00000000"; SIGNAL y_i : std_logic_vector (7 DownTo 0) := "00000000"; SIGNAL d_o : std_logic_vector (7 DownTo 0) := "00000000"; constant PERIOD : time := 40 ns; constant DUTY_CYCLE : real := 0.5; constant OFFSET : time := 10 ns; BEGIN UUT : Processor PORT MAP ( clk => clk, go_i => go_i, x_i => x_i, y_i => y_i, d_o => d_o ); PROCESS -- clock process for clk BEGIN WAIT for OFFSET; CLOCK_LOOP : LOOP clk <= '0'; WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE)); clk <= '1'; WAIT FOR (PERIOD * DUTY_CYCLE); END LOOP CLOCK_LOOP; END PROCESS; PROCESS BEGIN -- ------------- Current Time: 29ns WAIT FOR 29 ns; x_i <= "00001111"; y_i <= "00000101"; -- ------------------------------------- -- ------------- Current Time: 69ns WAIT FOR 40 ns; go_i <= '1'; -- ------------------------------------- -- ------------- Current Time: 109ns WAIT FOR 40 ns; go_i <= '0'; -- ------------------------------------- WAIT FOR 931 ns; END PROCESS; END testbench_arch;