---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 18:04:39 06/22/2010 -- Design Name: -- Module Name: Datapath - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Datapath is Port ( clk : in STD_LOGIC; x_sel : in STD_LOGIC; y_sel : in STD_LOGIC; x_ld : in STD_LOGIC; y_ld : in STD_LOGIC; d_ld : in STD_LOGIC; x_neq_y : out STD_LOGIC; x_lt_y : out STD_LOGIC; x_i : in STD_LOGIC_VECTOR (7 downto 0); y_i : in STD_LOGIC_VECTOR (7 downto 0); d_o : out STD_LOGIC_VECTOR (7 downto 0)); end Datapath; architecture Behavioral of Datapath is signal x_reg : STD_LOGIC_VECTOR (7 downto 0); signal y_reg : STD_LOGIC_VECTOR (7 downto 0); begin -- sequential statements main: process (clk) begin if rising_edge (clk) then if (d_ld = '1') then d_o <= x_reg; end if; if (x_ld = '1') then if (x_sel = '1') then x_reg <= x_reg - y_reg; else x_reg <= x_i; end if; end if; if (y_ld = '1') then if (y_sel = '1') then y_reg <= y_reg - x_reg; else y_reg <= y_i; end if; end if; if (x_reg = y_reg) then x_neq_y <= '0'; else x_neq_y <= '1'; end if; if (x_reg < y_reg) then x_lt_y <= '1'; else x_lt_y <= '0'; end if; end if; end process; end Behavioral;